EDN

Agere to pull Cadence partitioning, sign-off tool into ASIC flow

ALLENTOWN, Pa. — Agere Systems is working with San Jose, California-based Cadence Design Systems Inc. to provide Agere ASIC customers with access to Cadence's “First Encounter” EDA software. This is ...
Business Wire

Socionext Adopts the Cadence Full-Flow Digital and Signoff Tools for 7nm Designs

SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that Socionext used the Cadence ® full-flow digital and signoff tools for the successful production ...
Nasdaq

Global Unichip Corporation Uses Cadence Digital Implementation and Signoff Flow to Deliver Advanced-Node Designs for AI and HPC Applications

Cadence Innovus Implementation System and Voltus IC Power Integrity Solution enable GUC to achieve first-pass silicon success and meet GHz performance target for multi-billion gate designs Traditional ...
Business Wire

GUC Optimizes Quality of Results and Accelerates Time to Tapeout Using the Cadence Digital Full Flow

SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced Global Unichip Corporation (GUC) used the Cadence ® digital full flow to accelerate the time to tapeout ...
EDN

Cadence supports structured ASIC design

SANTA CRUZ, Calif. — Cadence Design Systems has announced that its SoC Encounter IC physical design platform is providing “back end” support for structured ASICs from both NEC Electronics and Faraday ...
Design-Reuse

VeriSilicon Joins Power Forward Initiative to Accelerate Advanced Low-Power Design

Leading ASIC and IP Provider to Offer CPF-Based Low-Power Solution SANTA CLARA, CA -- May 12, 2008 -- VeriSilicon Holdings Co., Ltd. (VeriSilicon), a world-class ASIC design foundry and custom ...
Business Insider

New Cadence Virtuoso System Design Platform Provides Seamless Design Flow Between IC, Package and Board

Solution integrates the Virtuoso platform with Allegro and Sigrity technologies to streamline overall design process and significantly improve productivity and cycle time SAN JOSE, Calif., May 30, ...
Hexus

Cadence Collaborates With IBM, Samsung & Chartered To Deliver 65-NM Reference Flow

Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic design innovation, today announced immediate availability of the 65-nanometer Common Power Format (CPF) enabled reference ...
Nasdaq

GUC Optimizes Quality of Results and Accelerates Time to Tapeout Using the Cadence Digital Full Flow

Cadence’s Innovus Implementation System mixed-placer automation delivers more than 10% wirelength reduction and 5% better switching power GUC reduces floorplan design time from weeks to days, ...