Design-Reuse

How to Reduce FPGA Logic Cell Usage by >x5 for Floating-Point FFTs

Here we provide rational for using Centar’s floating-point IP core for the new Altera Arria 10 and Stratix 10 FPGA platforms. After a short contextual discussion section, a comparison of various FFT ...
Design-Reuse

Systolic array verilog IP Listing

The I2C Controller IP Core implements an I2C Slave Controller, with a user parameterized Register Array or Memory (i.e SRAM / FIFO) or any Peripheral connecting on an AHB / APB / AXI / Avalon ... The ...
The Next Platform

Xilinx Unveils xDNN FPGA Architecture for AI Inference

FPGAs might not have carved out a niche in the deep learning training space the way some might have expected but the low power, high frequency needs of AI inference fit the curve of reprogrammable ...