IP that’s built on a RISC-V vector processing CPU. The platform has been augmented to support artificial-intelligence/machine ...

The modules themselves don’t have full-sized ports, but when connected to a carrier board like the Bit-Brick Cluster K1 you get access to Gigabit ethernet, HDMI 1.4, USB 3.0 and USB 2.0 Type-A ports, ...

The RISC-V Summit North America, held on 22-23 October 2025 in Santa Clara, California, showcased the latest CPU cores featuring new vector processors, high-speed interfaces, and peripheral subsystems ...

IAR Embedded Workbench is a commercial embedded development toolchain, known for powerful code optimisation and a reliable environment.

If you read Japanese, you might have seen the book “Design and Implementation of Microkernels” by [Seiya Nuda]. An appendix covers how to write your own operating system for RISC-V in about 1,000 ...

RISC-V, pronounced “risk five,” is a modern open-source instruction set architecture (ISA) based on reduced instruction set computer (RISC) principles. In simple terms, it’s like a blueprint that ...

The Government of India has announced the launch of the Linux-compatible DHRUV64 (VEGA AS2161) dual-core 64-bit RISC-V MPU ...

Forbes contributors publish independent expert analyses and insights. Dave Altavilla is a Tech Analyst covering chips, compute and AI. For decades, chip architectures have been dominated by a pair of ...

EVM still powers the ecosystem due to tooling, trust, and compatibility. Vitalik’s April 2025 proposal aims to replace the EVM with RISC-V, an open instruction set architecture. RISC-V offers ...

The 2024 RISC-V Summit North America marked a significant milestone for the RISC-V community with the ratification of the RVA23 Profile. This event signifies a major step forward in the evolution of ...

Have you ever wondered if there’s a way to break free from the dominance of proprietary computing architectures like x86 and ARM? For decades, these platforms have dictated the rules of the game, ...