Nature

Dynamic Scheduling and Decoding Algorithms for LDPC and Reed-Solomon Codes

Dynamic scheduling and decoding algorithms have become pivotal in advancing the performance of error-correcting codes. Recent innovations have focused on refining Low-Density Parity-Check (LDPC) codes ...
EDN

Low power LDPC decoder created using high level synthesis

HLS methodology allows the hardware design to be completed at a higher level of abstraction such as C/C++ algorithmic description. This provides significant time and cost savings, and paves the way ...
Design-Reuse

Stochastic Computation applied to the design of Error Correcting Decoders

We describe the application of stochastic computation to a family of error-correcting decoders. We have applied this technology to the Low Density Parity Check (LDPC ...
Design-Reuse

Unified C-programmable ASIP architecture for multi-standard Viterbi, Turbo and LDPC decoding

This paper describes an ASIP decoder template suitable for multi-standard Viterbi, Turbo and LDPC decoding. We show architecture fitness for WLAN, WiMAX and 3GPPLTE standards, although various other ...
TechRepublic

Low-Complexity Encoding of LDPC Codes: A New Algorithm and its Performance

A new technique for efficient encoding of LDPC codes based on the known concept of Approximate Lower Triangulation (ALT) is introduced. The greedy permutation algorithm is presented to transform ...